1. Field of the Invention
The present invention relates to non-volatile memory devices and, more particularly, to localized trapped charge memory cell structures capable of storing multiple bits per cell.
2. Description of Related Art
A non-volatile semiconductor memory device is designed to maintain programmed information even in the absence of electrical power. Read only memory (ROM) is a non-volatile memory commonly used in electronic equipment such as microprocessor-based digital electronic equipment and portable electronic devices such as cellular phones.
ROM devices typically include multiple memory cell arrays. Each memory cell array may be visualized as including intersecting word lines and bit lines. Each word and bit line intersection can correspond to one bit of memory. In mask programmable metal oxide semiconductor (MOS)ROM devices, the presence or absence of a MOS transistor at word and bit line intersections distinguishes between a stored logic ‘0’ and logic ‘1’.
A programmable read only memory (PROM) is similar to the mask programmable ROM except that a user may store data values (i.e., program the PROM) using a PROM programmer. A PROM device is typically manufactured with fusible links at all word and bit line intersections. This corresponds to having all bits at a particular logic value, typically logic ‘1’. The PROM programmer is used to set desired bits to the opposite logic value, typically by applying a high voltage that vaporizes the fusible links corresponding to the desired bits. A typical PROM device can only be programmed once.
An erasable programmable read only memory (EPROM) is programmable like a PROM, but can also be erased (e.g., to an all logic ‘1’s state) by exposing it to ultraviolet light. A typical EPROM device has a floating gate MOS transistor at all word and bit line intersections (i.e., at every bit location). Each MOS transistor has two gates: a floating gate and a non-floating gate. The floating gate is not electrically connected to any conductor, and is surrounded by a high impedance insulating material. To program the EPROM device, a high voltage is applied to the non-floating gate at each bit location where a logic value (e.g., a logic ‘0’) is to be stored. This causes a breakdown in the insulating material and allows a negative charge to accumulate on the floating gate. When the high voltage is removed, the negative charge remains on the floating gate. During subsequent read operations, the negative charge prevents the MOS transistor from forming a low resistance channel between a drain terminal and a source terminal (i.e., from turning on) when the transistor is selected.
An EPROM integrated circuit is normally housed in a package having a quartz lid, and the EPROM is erased by exposing the EPROM integrated circuit to ultraviolet light passed through the quartz lid. The insulating material surrounding the floating gates becomes slightly conductive when exposed to the ultraviolet light, allowing the accumulated negative charges on the floating gates to dissipate.
A typical electrically erasable programmable read only memory (EEPROM) device is similar to an EPROM device except that individual stored bits may be erased electrically. The floating gates in the EEPROM device are surrounded by a much thinner insulating layer, and accumulated negative charges on the floating gates can be dissipated by applying a voltage having a polarity opposite that of the programming voltage to the non-floating gates.
Flash memory devices are sometimes called flash EEPROM devices, and differ from EEPROM devices in that electrical erasure involves large sections of, or the entire contents of, a flash memory device.
A relatively recent development in non-volatile memory is localized trapped charge devices. While these devices are commonly referred to as nitride read only memory (NROM) devices, the acronym “NROM” is a part of a combination trademark of Saifun Semiconductors Ltd. (Netanya, Israel).
Each memory cell of a localized trapped charge array is typically an n-channel MOS (nMOS) transistor with an oxide-nitride-oxide (ONO) dielectric structure forming the gate dielectric. Data is stored in two separate locations adjacent to the source and drain terminals of the NMOS transistor, allowing 2 bits of data to be stored in the nMOS transistor structure. The localized trapped charge memory cells are typically programmed by channel hot electron (CHE) injection through bottom oxide layers of the ONO dielectric structures. During programming, electrical charge is trapped in the ONO dielectric structures. The localized trapped charge memory cells are erased by tunneling enhanced hot hole (TEHH) injection through bottom oxide layers of the ONO dielectric structures.
FIGS. 1A and 1B will now be used to illustrate a problem that arises in known localized trapped charge memory cell structures. FIG. 1A is a cross-sectional view of 2 known localized trapped charge memory cell structures 100A and 100B formed on and in a semiconductor substrate 102. The localized trapped charge memory cell structure 10A includes a first oxide-nitride-oxide (ONO) dielectric structure positioned between an electrically conductive gate terminal 104A of a first nMOS transistor structure and 2 buried source/drain regions 106A and 106B. The buried source/drain regions 106A and 106B form interchangeable source and drain regions of the first nMOS transistor structure. The first ONO dielectric structure includes a first silicon dioxide (oxide) layer 108A, a silicon nitride (nitride) layer 110A over the first oxide layer 108A, and a second oxide layer 112A over the nitride layer 1I A.
Similarly, the localized trapped charge memory cell structure 100B includes a second ONO dielectric structure positioned between an electrically conductive gate terminal 104B of a second nMOS transistor structure and 2 buried source/drain regions 106B and 106C. The buried source/drain regions 106B and 106C form interchangeable source and drain regions of the second nMOS transistor structure. The second ONO dielectric structure includes a first silicon dioxide (oxide) layer 108B, a silicon nitride (nitride) layer 110B over the first oxide layer 108B, and a second oxide layer 112B over the nitride layer 110B.
The buried source/drain regions 106A, 106B, and 106C form bit lines of the 2 localized trapped charge memory cell structures 100A and 100B. In a known method for forming the structure of FIG. 1, relatively thick oxide layers 114A, 114B, and 114C are grown over the respective buried source/drain regions 106A, 106B, and 106C to electrically isolate the buried source/drain regions 106A, 106B, and 106C from a word line (not shown) to be formed over the gate terminals 104A and 104B, and the oxide layers 114A, 114B, and 114C.
FIG. 1B illustrates a problem that arises in the known localized trapped charge memory cell structures 100A and 100B of FIG. 1A in that the oxide layers 114A, 114B, and 114C formed over the respective buried source/drain regions 106A, 106B, and 106C encroach into the two areas of the localized trapped charge memory cell structures 100A and 100B where data is stored, reducing data retention time and a maximum number of read/write cycles (i.e., endurance) of the memory cell structures.
FIG. 1B is a magnified view of a portion of FIG. 1A where the oxide layer 108A, the buried source/drain region 106B, and the oxide layer 114B meet. When the oxide layer 114B is grown over the buried source/drain region 106B, a pointed “bird's beak” structure 116 forms at an outer edge of the oxide layer 114B where the oxide layer 108A, the buried source/drain region 106B, and the oxide layer 114B meet. The localized trapped charge memory cell structure 100A stores one bit of data in this area. As shown in FIG. 1B, the bird's beak structure 116 extends a significant distance under a component stack of the localized trapped charge memory cell structure 100A, and can reduce the data retention time and the endurance of the corresponding portion of the localized trapped charge memory cell structure 100A.
It would thus be advantageous to have a localized trapped charge memory cell structure in which bird's beak structures like those shown in FIG. 1B are reduced or eliminated, and a method for forming such localized trapped charge memory cell structures.